1. Field of the Invention
The present invention relates to sigma-delta modulators used in analog-to-digital converters.
2. Related Art
Sigma-delta modulation is a noise shaping process that uses over-sampling and feedback to reduce the in-band quantization noise at the expense of boosting the noise outside the signal band of interest. This out-of-band noise is then filtered using digital filters. The extent of the noise shaping can be controlled by changing the order of the loop (L), which is the order of the high pass transfer function that shapes the noise, the over-sampling ratio (FCLK/2/FSIGNAL=M) and the number of levels in the quantizer (Q). FIG. 1 is a block diagram of a first order sigma-delta modulator (here, L=1). As shown in FIG. 1, the first order sigma-delta modulator includes a summing junction 101, an integrator 102, a quantizer 103, and a feedback DAC (digital to analog converter) 104, connected as shown. The Signal Transfer Function (STF) and Noise Transfer Function (NTF) of the first order sigma-delta modulator are defined as follows:STF=Y(z)/X(z)NTF=Y(z)/Q(z)
For a given L, M and Q there are different loop filter topologies to implement the NTF. Also, for a given set of specifications there are many different ways to implement a sigma-delta ADC (analog to digital converter).
The goal is to minimize the power and area when designing such a high order sigma-delta modulator with minimal design complexity. This becomes more important in fine line processes, where such ADC's are typically embedded inside a much larger chip, such as a single chip ADSL modem.
Higher order single loop architectures with single bit feedback have been used, which use both feedback and feed-forward loop filter topologies.
Their highly non-linear behavior makes it difficult to design stable modulators. Over load limit of single-bit delta-sigma modulators is inherently poor. Single bit delta-sigma modulators are unstable for signals significantly smaller than the full-scale reference, and have much lower dynamic range than ideally possible. Reference voltages need to be large, and KT/C noise from reference voltage capacitors is also large. This, in turn, results in increased noise for a given full-scale conversion, or larger power consumption and a lot of area taken up for the same noise performance.
Higher order single loop with feedback architecture and distributed multi-bit feedback DAC's have also been used (see, e.g., FIG. 2, showing an example implementation of a third order loop filter). The third order loop filter includes a number of summing junctions 101A–101C, a number of integrators 102A–102C, a quantizer 103, a number of feedback DAC's 104, all connected as shown. (Boxes with “a” and “b” represent multiplication by a constant). Such a structure typically results in very low gain in the first integrator 102A in FIG. 2. If the first integrator gain is low then the feedback capacitor will be large. For example: Gi=0.25→Cfb=Cin/Gi=4*Cin.
Multiple multibit DAC's are needed in the feedback path. Multi-bit DAC's need some sort of linearization scheme to maintain high linearity in the overall modulator. For multiple DAC's, this results in an added cost of linearization. First and second order single bit feedback stages can be cascaded, however, extremely high gain, high speed op amps for integrators (>80 dB over all corners) have to be used. It is difficult to achieve linearity over a large output dynamic range, and this approach often results in increased power consumption and area usage.
FIG. 3 shows a feed forward loop filter architecture that utilizes a summing junction 101, integrators 102A–102C, a quantizer 103, a feedback DAC 104, and a summer 301. Note that a single loop feed forward architecture with multi-bit feedback DAC's is shown in FIG. 3.
For the same third order loop filter used in FIG. 3, the feed forward architecture results in significantly higher gain for the first integrator and low attenuation in the signal path results in near ideal dynamic range. This results in significantly smaller integrator caps and hence smaller area.
Also, the integrator amplifiers have a smaller load and hence can be lower in power and area. Only one multi-bit feedback DAC is used.
The multi-bit quantizer has a linear gain, which improves the overload limit of the modulator and hence helps achieve near ideal dynamic range. Reference need not be over designed much larger than necessary. KT/C noise from reference capacitors is reduced. Fewer circuits (DAC's and linearization circuits) are needed, and the design of all integrators after the first is simplified, resulting in a lower area used by the circuit.
An extra summing amplifier is necessary before the flash quantizer (see FIG. 4). This puts tight timing constraints on the loop because of the delay through this stage. Large power and area overhead for this amplifier is needed, since the amplifier needs to accurately reproduce the outputs of all the integrators.
An n bit analog to digital converter (ADC) converts an analog voltage into one of 2n digital levels (represented by an “n” bit binary number, although sometimes n can be fractional, to result in a number of digital levels that is not a power of n, e.g., 17). A flash ADC uses 2n−1 comparators (an example is shown in FIG. 4 as comparator 401) simultaneously to compare the input voltage to all the 2n−1 reference levels and produces a thermometer-coded digital version of the input signal voltage (all the comparator 401 outputs for which the input is larger than the reference levels will be 1, and all the outputs for which the input signal is less than the reference levels will be 0). Each of the individual comparators 401 has 2 inputs and one output, and performs the following function:If V1>Vref→Y=1If V1<Vref→Y=0
where V1 is the input signal, Vref is the reference input to that comparator 101, and Y is the digital ouput of the comparator 401. In other words, FIG. 4 shows a conventional fully differential switched capacitor comparator 401. Here the input voltage (V1p, V1n) is sampled during phase 1 (φ1) on the capacitors (C1p, C1n) and in phase 2 (φ2) the same capacitors C1p, C1n are switched over to the reference voltage (Vrefp, Vrefn). The difference in charge ((V1p−V1n)*C1−(Vrefp−Vrefn)*C1 drives the summing junction of the comparator 401 positve or negative, and that is voltage amplified/regenerated in a latch inside the comparator 401 to generate the digital signal Y.
For a given noise specification, the input capacitors' C1p, C1n size is fixed based on KT/C noise and offset considerations.
The actual analog signal input to the flash ADC can be an algebraic expression of several other analog inputs:Y=A1*S1+A2*S2+A3*S3+A4*S4+. . .   (Equation 1)where A1, A2, A3 are constants and S1, S2, S3 are the various signals. A summing block is conventionally used to perform the algebraic function in equation 1, to result in a single output Y, which can then be digitized using a regular flash ADC. This summing amplifier needs to maintain the signal integrity to a high degree for precision applications, and is very power-hungry and requires significant area.